DocumentCode
2703184
Title
On applying set covering models to test set compaction
Author
Flores, Paulo F. ; Neto, Horácio C. ; Marques-Silva, João P.
Author_Institution
Cadence Eur. Labs., Inst. Superior Tecnico, Lisbon, Portugal
fYear
1999
fDate
4-6 Mar 1999
Firstpage
8
Lastpage
11
Abstract
Test set compaction is fundamental problem in digital system testing. In recent years, many competitive solutions have been proposed, most of which based on heuristics approaches. This paper studies the application of set covering models to the compaction of test sets, which can be used with any heuristic test set compaction procedure. For this purpose, recent and highly effective set covering algorithms are used. Experimental evidence suggests that the size of computed test sets can often be reduced by using set covering models and algorithms. Moreover a noteworthy empirical conclusion is that it may be preferable not to use fault simulation when the final objective is test set compaction
Keywords
automatic test pattern generation; integrated circuit testing; logic testing; minimisation; digital system testing; heuristic test set compaction; set compaction; set covering models; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Linear programming; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location
Ypsilanti, MI
ISSN
1066-1395
Print_ISBN
0-7695-0104-4
Type
conf
DOI
10.1109/GLSV.1999.757365
Filename
757365
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