Title :
Functional ATPG for delay faults
Author :
Tragoudas, S. ; Michael, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
This paper presents a functional level ATPG tool for delay faults which handles all existing fault models. The tool generates patterns using either binary decision diagrams or Boolean satisfiability. Experimental results are presented on the ISCAS´85 benchmarks
Keywords :
Boolean functions; VLSI; automatic test pattern generation; binary decision diagrams; delay estimation; fault diagnosis; integrated circuit testing; logic testing; Boolean satisfiability; ISCAS´85 benchmarks; binary decision diagrams; delay faults; fault models; functional ATPG; pattern generation; Automatic test pattern generation; Benchmark testing; Boolean functions; Circuit faults; Circuit testing; Data structures; Delay; Fiber reinforced plastics; Logic testing; Test pattern generators;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757367
