Title :
The design of a register renaming unit
Author :
Bishop, Benjamin ; Kelliher, Thomas P. ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations
Keywords :
SPICE; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; microprocessor chips; HSPICE-verified design; high-ILP processors; logic design; optimizations; register renaming unit; renaming hardware design; Computer science; Decoding; Educational institutions; Hardware; Instruction sets; Logic arrays; Programming profession; Random access memory; Shift registers; Systolic arrays;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757371
