Examining the required properties of build-up dielectric materials for next generation IC package substrates

Scaling of semiconductor chips have dramatically helped the increase in functionality of modern electronic and communication devices. However, this scaling also increased I/O count per unit area leading to necessity for smaller bumps and pitch sizes and finer trace pitches in flip chip substrates used in high end ICs. Furthermore, the requirement for lower warpage and change in thermal expansion of substrates during chip mounting is becoming more severe with the scaling of silicon due to the importance of interconnection reliability between the die and substrate. In addition, the need to suppress insertion loss is becoming more significant due to higher frequency of signals from increase in transmission speed. In this paper, properties of the newly developed build-up dielectric material, its manufacturability during substrate fabrication (Semi Additive Process compatibility) as well as how the properties of the dielectric material affected the overall package properties are discussed.