DocumentCode :
2703481
Title :
On optimizing test strategies for analog cells
Author :
Brosa, Anna M. ; Figueras, Joan
Author_Institution :
Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
fYear :
1999
fDate :
4-6 Mar 1999
Firstpage :
92
Lastpage :
96
Abstract :
The purpose of this paper is to analyze an optimization method to improve the testability of structural defects, such as bridges and opens, in low-power low-voltage analog circuits. The approach consists of finding an optimum subset of tests which maximizes the fault coverage with minimum cost. An application example is given to illustrate the proposal by studying the fault coverage obtained using different test sets on a simple 2-stage Nested Transconductance Capacitance Compensated (NGCC) amplifier
Keywords :
analogue integrated circuits; fault location; integrated circuit testing; low-power electronics; operational amplifiers; optimisation; 2-stage NGCC amplifier; analog cells; bridges; circuit testability; fault coverage; low-power analog circuits; low-voltage analog circuits; nested transconductance capacitance compensated amplifier; op amp testing; opens; optimization method; structural defects; test strategies optimisation; Analog circuits; Bridge circuits; Circuit faults; Circuit testing; Cost function; Electrical fault detection; Fabrication; Fault detection; Optimization methods; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
ISSN :
1066-1395
Print_ISBN :
0-7695-0104-4
Type :
conf
DOI :
10.1109/GLSV.1999.757384
Filename :
757384
Link To Document :
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