Title :
Package plane model validation using test chip, test package, and test board
Author :
Liao, J.C. ; Games, Ed
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
A test vehicle, which includes test chips, test packages, and a test board, has been developed for validation of the partial-element-equivalent-circuit (PEEC) plane inductance model. Actual noise level on the planes was measured and compared to that from modeling and simulation and the results are presented. The main features of the test vehicle as well as the validation procedure are also described
Keywords :
circuit analysis computing; equivalent circuits; inductance; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; integrated circuit testing; IC package plane model validation; PEEC network; high performance IC package; noise level; partial-element-equivalent-circuit plane inductance model; simulation; test board; test chip; test package; test vehicle; Backplanes; Inductance; Integrated circuit modeling; Integrated circuit packaging; Metallization; Monitoring; Noise level; Noise measurement; Testing; Variable structure systems;
Conference_Titel :
Electronic Components and Technology Conference, 1995. Proceedings., 45th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-2736-5
DOI :
10.1109/ECTC.1995.517780
