Title :
Low power multi-chains encoding scheme for SoC in low-cost environment
Author :
Wu, Po-Han ; Rau, Jiann-Chyi
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
Abstract :
In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels and less hardware for largest ISCAS´89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing (Wang and Chakrabarty, 2008) and our method. The average of improvement/ hardware is 16%/6%.
Keywords :
buffer circuits; data compression; encoding; low-power electronics; system-on-chip; SoC; buffers; compression architecture; low power multi-chains encoding; Circuit testing; Encoding; Feeds; Filling; Filters; Frequency; Hardware; Logic; Power dissipation; Very large scale integration;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355633
