Title :
A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface
Author :
Yuminaka, Yasushi ; Kawano, Kyohei
Author_Institution :
Dept. of Electron. Eng., Gunma Univ., Kiryu, Japan
Abstract :
This paper describes a ternary partial-response signaling scheme for capacitively coupled chip-to-chip data transmission to increase data rate. Partial-response coding is known as a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowing controlled intersymbol interference (ISI). Analysis and circuit simulation results are presented that compare this approach to two types of partial-response signaling, ternary duobinary (1+D) and dicode (1-D) signaling for capacitively coupled interface.
Keywords :
circuit simulation; data communication; high-speed integrated circuits; intersymbol interference; multiprocessor interconnection networks; partial response channels; system buses; capacitively coupled interface; chip-to-chip data transmission; circuit simulation; dicode signaling; frequency bandwidth; high-speed transmission; intersymbol interference; partial-response coding; ternary duobinary signaling; ternary partial-response signaling scheme; Bandwidth; Coaxial cables; Coupling circuits; Data communication; Data engineering; Frequency; Intersymbol interference; Partial response signaling; Signal analysis; Voltage; Capacitively Coupled Interface; Dicode; Duobinary; Equalizer; Partial-Response Signaling;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2010 40th IEEE International Symposium on
Conference_Location :
Barcelona
Print_ISBN :
978-1-4244-6752-5
DOI :
10.1109/ISMVL.2010.67
