• DocumentCode
    2703649
  • Title

    Efficient algorithms for finding highly acceptable designs based on module-utility selections

  • Author

    Chantrapornchai, Chantana ; Sha, Edwin H M ; Hu, Xiaobo

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    128
  • Lastpage
    131
  • Abstract
    In this paper we present an iterative framework to solve module selection problem under resource, latency, and power constraints. The framework associates a utility measure with each module. This measurement reflects the usefulness of the module for a given a design goal. Using modules with high utility values will result in superior designs. We propose a heuristic which iteratively perturbs module utility values until they tend to good module selections. Our experiments show that the module selections formed by combinations of modules with high utility values are superior solutions. Further by keeping modules with high utility values, the module exploration space can drastically be reduced
  • Keywords
    VLSI; circuit CAD; high level synthesis; integrated circuit design; iterative methods; modules; scheduling; VLSI; high-level synthesis; iterative framework; latency constraints; module exploration space; module selection problem; module-utility selections; power constraints; resource constraints; scheduling; utility measure; utility values; Algorithm design and analysis; Computer science; Delay; Flow graphs; Genetic algorithms; High level synthesis; Nominations and elections; Optimization methods; Space exploration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757393
  • Filename
    757393