An integrated approach for synthesizing LUT networks

Author

Yamashita, Shigeru ; Sawada, Hiroshi ; Nagoya, Akira

Author_Institution

Commun. Sci. Labs., NTT, Kyoto, Japan

fYear

1999

fDate

4-6 Mar 1999

Firstpage

136

Lastpage

139

Abstract

This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many decomposition methods that are not only algebraic but also functional are integrated. Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The experimental results are very encouraging

Keywords

field programmable gate arrays; logic CAD; multivalued logic circuits; table lookup; FPGAs; LUT networks; decomposition methods; lookup table networks; multilevel logic synthesis; network synthesis; Costs; Data structures; Field programmable gate arrays; Kernel; Laboratories; Libraries; Logic functions; Network synthesis; Programmable logic arrays; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757395

Filename

757395

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2703674