Title :
An integrated approach for synthesizing LUT networks
Author :
Yamashita, Shigeru ; Sawada, Hiroshi ; Nagoya, Akira
Author_Institution :
Commun. Sci. Labs., NTT, Kyoto, Japan
Abstract :
This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many decomposition methods that are not only algebraic but also functional are integrated. Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The experimental results are very encouraging
Keywords :
field programmable gate arrays; logic CAD; multivalued logic circuits; table lookup; FPGAs; LUT networks; decomposition methods; lookup table networks; multilevel logic synthesis; network synthesis; Costs; Data structures; Field programmable gate arrays; Kernel; Laboratories; Libraries; Logic functions; Network synthesis; Programmable logic arrays; Table lookup;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757395
