DocumentCode :
270370
Title :
A noise bifurcation architecture for linear additive physical functions
Author :
Meng-Day Yu ; Verbauwhede, Ingrid ; Devadas, Srinivas ; M´Raïhi, David
Author_Institution :
Verayo, Inc., San Jose, CA, USA
fYear :
2014
fDate :
6-7 May 2014
Firstpage :
124
Lastpage :
129
Abstract :
Physical Unclonable Functions (PUFs) allow a silicon device to be authenticated based on its manufacturing variations using challenge/response evaluations. Popular realizations use linear additive functions as building blocks. Security is scaled up using non-linear mixing (e.g., adding XORs). Because the responses are physically derived and thus noisy, the resulting explosion in noise impacts both the adversary (which is desirable) as well as the verifier (which is undesirable). We present the first architecture for linear additive physical functions where the noise seen by the adversary and the noise seen by the verifier are bifurcated by using a randomized decimation technique and a novel response recovery method at an authentication verification server. We allow the adversary´s noise ηa → 0.50 while keeping the verifier´s noise ηv constant, using a parameter-based authentication modality that does not require explicit challenge/response pair storage at the server. We present supporting data using 28nm FPGA PUF noise results as well as machine learning attack results. We demonstrate that our architecture can also withstand recent side-channel attacks that filter the noise (to clean up training challenge/response labels) prior to machine learning.
Keywords :
electronic engineering computing; explosions; field programmable gate arrays; learning (artificial intelligence); security; FPGA PUF noise; PUFs; authentication verification server; building blocks; challenge/response evaluations; explosion; linear additive functions; linear additive physical functions; machine learning attack; manufacturing variations; noise bifurcation architecture; noise impacts; nonlinear mixing; parameter-based authentication modality; physical unclonable functions; randomized decimation technique; response recovery method; security; side-channel attacks; silicon device; size 28 nm; Convergence; Field programmable gate arrays; Manufacturing; Reliability; Servers; Architecture; Authentication; Machine Learning; Physical Security; Side Channel;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2014 IEEE International Symposium on
Conference_Location :
Arlington, VA
Print_ISBN :
978-1-4799-4114-8
Type :
conf
DOI :
10.1109/HST.2014.6855582
Filename :
6855582
Link To Document :
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