Novel boundary scan circuit and methodology for ECL/BiCMOS VLSI

Author

Shookhtim, Rimon ; Lee, Lo-Shan ; Mansoorian, Babak ; Rothenberger, Roland ; Pond, Gil

Author_Institution

Unisys Corp., San Diego, CA, USA

fYear

1990

fDate

17-18 Sep 1990

Firstpage

128

Lastpage

131

Abstract

The authors introduce a novel technique which combines specially designed ECL (emitter coupled logic) and CMOS circuitry to produce a BiCMOS boundary scan circuit suitable for high-performance BiCMOS and ECL VLSI chips. A circuit description is given, and attention is given to system operation and to observability and controllability aspects. The layout of the BiCMOS scan chain element is shown

Keywords

BIMOS integrated circuits; VLSI; circuit layout; emitter-coupled logic; integrated logic circuits; BiCMOS scan chain element; ECL/BiCMOS VLSI; boundary scan circuit; controllability; design for testability; layout; logic diagram; observability; system operation; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Clocks; Flip-flops; Latches; Logic testing; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1990.171144

Filename

171144

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2703727