DocumentCode :
2703788
Title :
Minimizing outlier delay test cost in the presence of systematic variability
Author :
Drmanac, D. ; Bolin, Brendon ; Wang, Li C. ; Abadir, Magdy S.
Author_Institution :
Univ. of California, Santa Barbara, CA, USA
fYear :
2009
fDate :
1-6 Nov. 2009
Firstpage :
1
Lastpage :
10
Abstract :
This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information content measurements guide test clock selection. Exhaustive simulation found trade-offs between reducing the number of clocks, patterns, and chip samples. Substantial cost reduction was obtained with proper clock selection, while minimizing both test patterns and circuit samples required for effective outlier analysis.
Keywords :
Monte Carlo methods; clocks; cost reduction; delays; digital integrated circuits; entropy; integrated circuit testing; support vector machines; Monte Carlo simulations; cost reduction; entropy measures; outlier delay test cost minimization; support vector machine outlier analysis algorithms; systematic variability; test clocks; Algorithm design and analysis; Circuit simulation; Circuit testing; Clocks; Costs; Delay; Entropy; Semiconductor device measurement; Support vector machines; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
Type :
conf
DOI :
10.1109/TEST.2009.5355643
Filename :
5355643
Link To Document :
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