• DocumentCode
    2703869
  • Title

    Deep pipelines vs. risk and power walls [microprocessors]

  • Author

    Colwell, Bob

  • fYear
    2005
  • fDate
    14-16 March 2005
  • Abstract
    Summary form only given. Intel´s ×86 processors pushed pipelining and clock rates until physics stopped us. Less obviously, we were also pushing complexity, and therefore risk. We now know where the limits to these trends lie: with the Prescott processor. This talk explores the nature of risk in chip developments, how the ever-deepening pipelines in the Pentium series affected, and were affected by, perceived risk and thermals, and where the future will take us.
  • Keywords
    circuit complexity; integrated circuit design; microprocessor chips; pipeline processing; risk analysis; Pentium processors; Prescott processor; chip development risks; clock rates; complexity; deep pipelines; pipelining; power walls; thermal effects; Clocks; Physics; Pipeline processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on
  • ISSN
    1522-8681
  • Print_ISBN
    0-7695-2305-6
  • Type

    conf

  • DOI
    10.1109/ASYNC.2005.17
  • Filename
    1402040