DocumentCode
2703886
Title
Analysis of minimization algorithms for multiple-valued programmable logic arrays
Author
Tirumalai, Parthasarathy ; Butler, Jon T.
Author_Institution
Hewlett-Packard Co., Santa Clara, CA, USA
fYear
1988
fDate
0-0 1988
Firstpage
226
Lastpage
236
Abstract
The authors compare the performance of three heuristic algorithms for the minimization of sum-of-products expressions realized by the H.G. Kerkhoff and J.T. Butler´s (1986) multiple-valued programmable logic arrays. Heuristic methods are important because exact minimization is extremely time-consuming. The authors compare the heuristics to the exact solution, showing that heuristic methods are reasonably close to minimal. They use as a basis of comparison the average number of product terms over a set of randomly generated functions. All three heuristics produce nearly the same average number of product terms. Although the averages are close, there is surprisingly little overlap among the set of functions for which the best realization is achieved. Thus, there is a benefit to applying different heuristics and then choosing the best realization.<>
Keywords
cellular arrays; logic design; many-valued logics; minimisation; heuristic algorithms; minimization algorithms; multiple-valued programmable logic arrays; randomly generated functions; sum-of-products expressions; Algorithm design and analysis; Ducts; Government; Heuristic algorithms; Minimization methods; Noise measurement; Programmable logic arrays; Protection; Random number generation; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on
Conference_Location
Palma de Mallorca, Spain
Print_ISBN
0-8186-0859-5
Type
conf
DOI
10.1109/ISMVL.1988.5178
Filename
5178
Link To Document