• DocumentCode
    2703956
  • Title

    Model evaluation using genetic manipulation techniques

  • Author

    Stamenkovic, Z. ; Dahmen, H.-Ch. ; Glaeser, U.

  • Author_Institution
    Fac. of Electron. Eng., Nis Univ., Serbia
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    224
  • Lastpage
    225
  • Abstract
    Formal verification is an important area in industry getting more and more attention. Growing complexity of digital circuits and the use in safety critical systems are the reasons for the need of tools for checking the correctness of designs. In this paper we present a new approach for model evaluation. With our approach we are able to increase the belief of a designer in the right functionality of a circuit without the long runtimes of classical model checking but with more reliability than testing a design via simulation with some input patterns. To achieve this goal we use our genetic manipulation technique: a combination of classical genetic algorithms with a goal oriented mutation operator
  • Keywords
    VLSI; formal verification; genetic algorithms; hardware description languages; integrated circuit design; logic CAD; formal verification; functionality; genetic manipulation techniques; goal oriented mutation operator; input patterns; model evaluation; safety critical systems; Algorithm design and analysis; Analytical models; Circuit simulation; Circuit synthesis; Circuit testing; Counting circuits; Flowcharts; Genetic algorithms; Genetic mutations; Pattern analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757415
  • Filename
    757415