• DocumentCode
    2704031
  • Title

    A PC program that generates a model of the parasitics for BGA packages

  • Author

    Caggiano, Michael F.

  • Author_Institution
    AT&T Bell Labs., Allentown, PA, USA
  • fYear
    1995
  • fDate
    21-24 May 1995
  • Firstpage
    959
  • Lastpage
    963
  • Abstract
    The Package Parasitic Model Program is a PC program, that can generate a model of the parasitics for either two layer low cost BGA packages or for multi-layer high performance BGA packages. The user enters simple dimensional information for the geometry´s of the package from the package drawings. This information is easy to obtain from package dimensions or the program can default values for some of the more common dimensions, if their values are unknown. There are two files generated as outputs of the program. One file is a table containing all of the leads with each of the lead´s parasitics listed along with the input data and some of the calculated dimensions. The other file generated is a “SPICE deck”. This file contains all the leads´ parasitics in the form of a circuit topology that can be used as input for a SPICE simulation. The Package Parasitic Model Program is helpful in integrated circuit package design and analysis by delivering a model of package parasitics within a few seconds. This program saves the time of tedious data entry required in the more sophisticated three dimensional programs that require large amounts of CPU time on work stations
  • Keywords
    SPICE; circuit CAD; circuit analysis computing; integrated circuit design; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; microcomputer applications; PC program; Package Parasitic Model Program; SPICE simulation; analysis; circuit topology; dimensional information; integrated circuit package design; multilayer high performance BGA packages; package dimensions; two layer low cost BGA packages; Bonding; Capacitance; Computer simulation; Costs; Equations; Inductance; Integrated circuit modeling; Integrated circuit packaging; Routing; SPICE;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 1995. Proceedings., 45th
  • Conference_Location
    Las Vegas, NV
  • Print_ISBN
    0-7803-2736-5
  • Type

    conf

  • DOI
    10.1109/ECTC.1995.517806
  • Filename
    517806