DocumentCode :
2704035
Title :
Self-timed circuitry for global clocking
Author :
Fairbanks, Scott ; Moore, Simon
Author_Institution :
Cambridge Univ., UK
fYear :
2005
fDate :
14-16 March 2005
Firstpage :
86
Lastpage :
96
Abstract :
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Self-timed circuitry both generates and distributes a clock signal, while using less power and less skew compared to a clock tree. HSpice simulations, in a 180 nm CMOS process, comparing the distributed clock generator presented in this paper and an H-tree clock distribution system, each clocking a 16 mm×16 mm area suggests a 30% power savings. Also worst case skew was reduced from 27 ps to 2 ps while using a clock period equivalent to 9 FO4 gates.
Keywords :
CMOS logic circuits; asynchronous circuits; clocks; logic design; synchronisation; timing circuits; 16 mm; 180 nm; 2 ps; 27 ps; CMOS; Dynamic asP; FIFO; H-tree clock distribution system; clock distribution; distributed clock generator; global clocking; self-timed circuitry; synchronization; timing reference; worst case skew reduction; Circuit topology; Clocks; Delay; Digital systems; Frequency; Logic gates; Power generation; Signal generators; Timing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on
ISSN :
1522-8681
Print_ISBN :
0-7695-2305-6
Type :
conf
DOI :
10.1109/ASYNC.2005.29
Filename :
1402049
Link To Document :
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