VHDL design of a test processor based on mixed-mode test generation

This paper presents the VHDL design of a prototype test processor, which can be used for functional testing of digital ICs. The design of the test processor supports itself to be controlled by a microcomputer. The processor can generate mixed-mode (pseudo-random followed by deterministic) test vectors and can apply them to circuit under test (CUT). The test processor also receives the output responses of the CUT and compresses them to a signature. The signature is then sent to the computer for comparison. The test processor supports the testing of combinational as well as sequential circuits (with scanpath)