A high-speed low-power JFET pull-down ECL circuit

Author

Shin, Hyun J. ; Lu, P.F. ; Chuang, C.T.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1990

fDate

17-18 Sep 1990

Firstpage

136

Lastpage

139

Abstract

A high-speed low-power ECL (emitter coupled logic) circuit with an active pull-down output stage that utilizes a `free´ JFET (junction FET) available in any n-p-n bipolar technology is described. The JFET pull-down output stage operates as a push-pull follower stage and enhances both the speed and load driving capability. Simulation results based on an 0.8-μm double-poly self-aligned bipolar technology indicate that the circuit with a typical loading at a power consumption of 1 mW per gate offers 24% improvement in the pull-down delay and 53% improvement in the load driving capability compared with the conventional ECL circuit

Keywords

emitter-coupled logic; integrated logic circuits; junction gate field effect transistors; monolithic integrated circuits; 0.8 micron; BiFET IC; ECL circuit; JFET pull-down output stage; emitter coupled logic; high-speed; junction FET; low-power; push-pull follower stage; self-aligned bipolar technology; Circuit simulation; Current measurement; Delay; Electrical resistance measurement; Energy consumption; JFET circuits; Power dissipation; Resistors; Steady-state; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1990.171146

Filename

171146