BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor

Author

Ekanayake, Virantha N. ; Kelly, Clinton, IV ; Manohar, Rajit

Author_Institution

Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

fYear

2005

fDate

14-16 March 2005

Firstpage

144

Lastpage

154

Abstract

We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the sensor network asynchronous processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180 nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152 pJ/ins at 1.8 V and just 17 pJ/ins at 0.6 V.

Keywords

CMOS logic circuits; asynchronous circuits; low-power electronics; microprocessor chips; wireless sensor networks; 0.6 V; 1.8 V; 180 nm; 6 to 54 MIPS; BitSNAP; CMOS processor; SNAP ISA; asynchronous processor; bit-serial datapaths; datapath energy consumption reduction; dynamic significance compression; low-energy sensor network; wireless sensor-network node; Asynchronous circuits; Computer architecture; Computer networks; Energy consumption; Hardware; Instruction sets; Microcontrollers; Network-on-a-chip; Process design; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on

ISSN

1522-8681

Print_ISBN

0-7695-2305-6

Type

conf

DOI

10.1109/ASYNC.2005.14

Filename

1402056