• DocumentCode
    2704199
  • Title

    Formal checking of properties in complex systems using abstractions

  • Author

    Moundanos, Dinos ; Abraham, Jacob A.

  • Author_Institution
    Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    280
  • Lastpage
    283
  • Abstract
    Only very small designs can be verified currently using property checking due to state-space explosion. Abstractions have been developed to simplify the design in an attempt to address this problem. However, the properties themselves may involve large state spaces, and practical property checking is generally confined to the control behavior. This paper describes an elegant technique for verifying properties of complex designs where the abstraction is applied to both the property and the design, thereby allowing us to verify properties which may deal with the data space. We demonstrate the technique on a processor by checking properties which are intractable using existing model checking techniques
  • Keywords
    Boolean functions; VLSI; formal verification; integrated circuit design; logic CAD; state-space methods; Boolean logic level; IC design; VLSI; abstractions; complex systems; data space; formal checking; formal verification; model checking techniques; state-space explosion; Boolean functions; Circuits; Design engineering; Electronic switching systems; Formal verification; Jacobian matrices; Logic design; Space technology; State-space methods; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757433
  • Filename
    757433