Title :
New wiring design concept for reducing wiring resistance effect in ECL circuit
Author :
Oda, N. ; Ohtake, T. ; Takemura, H. ; Tashiro, T.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A novel wiring design concept called the wire width optimization relating to wire length (WORWIL) method is presented to alleviate wiring delay increase. The problems of increasing interconnection wiring delay due to the wiring resistance in high-performance ECL (emitter coupled logic) circuits and the limitation of the wire utility ratio are solved by this method. Some case studies were performed to confirm the validity of this method. Because of its generality and simplicity, the WORWIL method should be applicable to all types of VLSI design
Keywords :
VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; ECL circuit; WORWIL method; emitter coupled logic; interconnection wiring delay; wire length; wire width optimization; wiring design; wiring resistance reduction; Circuit simulation; Delay effects; Integrated circuit interconnections; Length measurement; National electric code; Semiconductor device measurement; Statistical distributions; Very large scale integration; Wire; Wiring;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1990.171147
