Title :
Fast extended test access via JTAG and FPGAs
Author :
Devadze, Sergei ; Jutman, Artur ; Aleksejev, I. ; Ubar, Raimund
Author_Institution :
Testonica Lab. OU, Tallinn, Estonia
Abstract :
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard boundary scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.
Keywords :
boundary scan testing; field programmable gate arrays; printed circuit manufacture; printed circuit testing; FPGA; JTAG; boundary scan; electronic manufacturing; manufacturing defects; printed circuit boards; system-level testing; test access mechanism; test access protocol; Access protocols; Circuit testing; Design for testability; Electronic equipment testing; Field programmable gate arrays; Frequency; Performance evaluation; Printed circuits; Pulp manufacturing; System testing;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355668
