Title :
NMOS energy recovery logic
Author :
Kim, Chulwoo ; Yoo, Seung-Moon ; Sung-Mo Kiang
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping techniques. NERL shows full output voltage swing, insensitivity to output load capacitance, less dependency on power-clock frequency and complementary outputs for balanced capacitance load to power-clock. We have designed an 8-bit CLA and inverter chain using 0.6 μm CMOS technology and verified that NERL saves energy over ECRL by 2 to 3 times
Keywords :
MOS logic circuits; adders; capacitance; logic gates; low-power electronics; 0.6 micron; CMOS technology; NMOS energy recovery logic; adiabatic logic circuits; bootstrapping; carry lookahead adder; complementary outputs; efficient energy transfer; high throughput; inverter chain; low energy consumption; CMOS technology; Capacitance; Energy consumption; Energy exchange; Frequency; Inverters; Logic; MOS devices; Throughput; Voltage;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757440
