Title :
A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL
Author :
Ishibashi, Koji ; Komiyaji, K. ; Toyoshima, Hisashi ; Minami, Mamoru ; Ooki, N. ; Ishida, Hiroto ; Yamanaka, T. ; Nagano, F. ; Nishida, Tsutomu
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
This 4 Mb (64 k/spl times/64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25 /spl mu/m CMOS for cache memories. It achieves fully-random 300 MHz operation at a 2.5 V supply. The bandwidth is 2.4 GB/s; the highest value reported. This frequency is achieved through multi-phase active pulse control (MPAC), in which active pulse signals generated by a multi-phase PLL control the SRAM data path. The longest data path delay is shortened by dynamic decoders and current sense amplifiers.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; digital phase locked loops; memory architecture; pipeline processing; 0.25 micron; 2.5 V; 300 MHz; 4 Mbit; cache memories; current sense amplifiers; data path delay; dynamic decoders; multi-phase PLL; multi-phase active pulse control; synchronous wave-pipeline CMOS SRAM; Bandwidth; Cache memory; Decoding; Delay; Frequency; Phase locked loops; Pulse amplifiers; Pulse generation; Random access memory; Signal generators;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535568
