Exploiting test resource optimization in data path synthesis for BIST

Author

Li, Xiaowei ; Cheung, Paul Y S

Author_Institution

Dept. of Comput. Sci. & Technol., Beijing Univ., China

fYear

1999

fDate

4-6 Mar 1999

Firstpage

342

Lastpage

343

Abstract

Area and test time are two major overheads encountered during data path synthesis for BIST. This paper presents an attempt towards testability enhancement in data path BIST synthesis by considering two factors simultaneously. It is achieved by incorporating two testability constraints in data path synthesis. Experimental results are presented to demonstrate the effectiveness of the proposed (data path) BIST synthesis approach

Keywords

VLSI; automatic test pattern generation; built-in self test; design for testability; integer programming; integrated circuit testing; linear programming; optimisation; BIST; area; data path synthesis; overheads; test resource optimization; test time; testability constraints; testability enhancement; Benchmark testing; Built-in self-test; Computer science; Concurrent computing; Costs; Integer linear programming; Logic testing; Performance evaluation; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757451

Filename

757451

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2704522