Title :
A multilevel cache memory architecture for nanoelectronics
Author_Institution :
Dept. of Phys. & Astron., Univ. Coll. London, UK
Abstract :
In this paper, the author presents a new multilevel cache memory architecture which uses only near-neighbour connections, thus eliminating long tracks and rendering the system suitable for nanoelectronic implementation. Operation of the memory is such that the most-recently accessed data is kept closest to the read-write port
Keywords :
cache storage; integrated memory circuits; memory architecture; nanotechnology; multilevel cache memory architecture; nanoelectronic implementation; near-neighbour connections; Astronomy; Cache memory; Educational institutions; Electrical capacitance tomography; Image processing; Memory architecture; Nanoelectronics; Physics; Propagation delay; Read-write memory;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757453
