A 1.8 V high dynamic-range CMOS high-speed four quadrant multiplier

Author

Lin, Chi-Hung ; Ismail, Mohammed

Author_Institution

Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA

fYear

1999

fDate

4-6 Mar 1999

Firstpage

372

Lastpage

375

Abstract

A low-voltage (⩽3 V) CMOS four quadrant multiple is introduced which has an almost rail-to-rail differential-input-swing with a low signal-distortion (⩽1% for 100 kHz signal). The proposed circuit is composed of a pair of rail-to-rail differential-input V-I converters and a pair of voltage-followers. This topology of multiplier results in a high frequency capability with low power consumption. In a 1.2 μm n-well CMOS process, the 3 dB frequency of the multiplier is in a range of 103 MHz. Measured total power consumption is around 0.52 mW with supply voltage 2 V. The multiplier can operate at a minimum supply voltage of 1.8 V

Keywords

CMOS analogue integrated circuits; analogue multipliers; high-speed integrated circuits; low-power electronics; 0.52 mW; 1.2 micron; 1.8 to 3 V; 103 MHz; CMOS high-speed analog multiplier; differential-input V-I converters; four quadrant multiplier; high dynamic-range; high frequency capability; low power consumption; low signal-distortion; low-voltage operation; n-well CMOS process; rail-to-rail differential-input-swing; voltage-followers; CMOS process; Circuit topology; Energy consumption; Feedback loop; Frequency; Low voltage; MOSFETs; Power measurement; Signal processing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757459

Filename

757459