DocumentCode :
2704676
Title :
Test point insertion using functional flip-flops to drive control points
Author :
Yang, Joon-Sung ; Nadeau-Dostie, Benoit ; Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
fYear :
2009
fDate :
1-6 Nov. 2009
Firstpage :
1
Lastpage :
10
Abstract :
This paper presents a novel method for reducing the area overhead introduced by test point insertion. Test point locations are calculated as usual using a commercial tool. However, the proposed method uses functional flip-flops to drive control test points instead of test-dedicated flip-flops. Logic cone analysis that considers the distance and path inversion parity from candidate functional flip-flops to each control point is used to select an appropriate functional flip-flop to drive the control point which avoids adding additional timing constraints. Reconvergence is also checked to avoid degrading the testability. Experimental results indicate that the proposed method significantly reduces test point area overhead and achieves essentially the same fault coverage as the implementations using dedicated flip-flops driving the control points.
Keywords :
circuit testing; flip-flops; timing; control test points; distance inversion parity; functional flip-flops; logic cone analysis; path inversion parity; reconvergence; test point area overhead; test point insertion; testability; timing constraints; Built-in self-test; Circuit faults; Circuit testing; Drives; Electrical fault detection; Fault detection; Flip-flops; Life testing; Logic testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
Type :
conf
DOI :
10.1109/TEST.2009.5355688
Filename :
5355688
Link To Document :
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