Title :
Memory chip BIST architecture
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is “free” for some faults during test. 4. Is never subject to aliasing. 5. Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as a built-in feature, it does not slow down the normal operation of the array. 7. Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. 8. If used as a built-in feature, the hardware overhead is very low
Keywords :
built-in self test; fault diagnosis; integrated circuit testing; random-access storage; RAM chip; array test scheme; built-in mode; decoder faults; fault diagnosis; memory chip BIST architecture; off chip/module mode; pattern-sensitive faults; random access memory; shorts; stuck-cells; Built-in self-test; Circuit faults; Costs; Decoding; Failure analysis; Fault detection; Fault diagnosis; Hardware; Memory architecture; Testing;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757462
