DocumentCode
2704771
Title
A fully pipelined, 700 MBytes/s DES encryption core
Author
Kim, Ihn ; Steele, Craig S. ; Koller, Jefferey G.
Author_Institution
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
fYear
1999
fDate
4-6 Mar 1999
Firstpage
386
Lastpage
387
Abstract
Fully-pipelined, 56-bit DES de/encryption and authentication at memory-bus bandwidths is now feasible. We describe a custom, 7 square mm, 120 mW core in 4-metal 0.35 μm CMOS. Performance allows on-the-fly encryption of 64-bit, 66 MHz PCI traffic, and hence typical network traffic. FPGA, synthesized, and 3-metal versions are compared
Keywords
CMOS digital integrated circuits; VLSI; application specific integrated circuits; cryptography; digital signal processing chips; pipeline processing; 0.35 micron; 120 mW; 4-metal CMOS process; 56 bit; 64 bit; 66 MHz; 700 MByte/s; DES encryption core; Data Encryption Standard; PCI traffic; authentication; custom chip; fully pipelined architecture; network traffic; Circuits; Clocks; Cryptography; Delay; Field programmable gate arrays; Logic devices; Routing; Silicon; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location
Ypsilanti, MI
ISSN
1066-1395
Print_ISBN
0-7695-0104-4
Type
conf
DOI
10.1109/GLSV.1999.757463
Filename
757463
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