Transistor stuck-open fault detection in multilevel CMOS circuits

Author

Abd-El-Barr, Mostafa ; Xu, Yanging ; McCrosky, Carl

Author_Institution

Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

fYear

1999

fDate

4-6 Mar 1999

Firstpage

388

Lastpage

391

Abstract

The necessary and sufficient conditions for detecting transistor stuck-open faults in arbitrary multilevel CMOS circuits are shown. A method for representing a two-pattern test for detecting a single stuck-open fault using only one cube is presented. The relationship between the D-algorithm and the conditions for detecting transistor stuck-open faults in CMOS circuits is provided. The application of the proposed approach in robust test generation for transistor stuck-open faults in a number of benchmark circuits is demonstrated. The fault coverage achieved is as good as or better than those reported using existing techniques

Keywords

CMOS logic circuits; automatic test pattern generation; fault location; integrated circuit testing; logic testing; multivalued logic circuits; D-algorithm; fault coverage; multilevel CMOS circuits; robust test generation; transistor stuck-open fault detection; two-pattern test; Benchmark testing; Circuit faults; Circuit testing; Computer science; DH-HEMTs; Electrical fault detection; Fault detection; Minerals; Robustness; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757464

Filename

757464