Title :
A 1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits
Author :
Hanyu, T. ; Mochizuki, A. ; Kameyama, M.
Author_Institution :
Tohoku Univ., Sendai, Japan
Abstract :
This paper presents the design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation.
Keywords :
MOS logic circuits; multiplying circuits; multivalued logic circuits; pipeline arithmetic; 1.5 V; 200 MHz; arithmetic system; low-power high-speed operation; multiple-valued current-mode MOS differential logic circuits; pipelined multiplier; Adders; Arithmetic; Delay; Detectors; Inverters; Logic circuits; Low voltage; Power dissipation; Switching circuits; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535570
