DocumentCode :
2705043
Title :
Application of BSG films as interlevel dielectric in a 1 μm DLM process
Author :
Rey, A. ; Lesaicherre, P.-Y. ; Pourquier, E.
Author_Institution :
Thomson Composants Militaires et Spatiaux, Saint Egreve, France
fYear :
1990
fDate :
12-13 Jun 1990
Firstpage :
393
Lastpage :
395
Abstract :
Summary form only given. Borosilicate glass (BSG) films were deposited in an atmospheric-pressure chemical vapor deposition (CVD) system. The best step coverage capabilities of BSG films were obtained for a 5% boron concentration and an oxygen/hydride ratio of 70/1. In these process conditions, various BSG film thicknesses were deposited on test structures composed of metal lines with different spacings, thicknesses, and sidewall profiles. The step coverage results are plotted on dimensionless diagrams. The limit curve of void formation and abacus of equal lateral step coverage are shown for two metal profiles. The planarization of the BSG films, realized by etchback with a spin-on-glass (SOG) layer, was studied on test structures. With any BSG thicknesses or etchback quantities, a planarization with a total SOG sacrificial layer without void formation is possible only when the aspect ratio is lower than the previous limit. A BSG interlevel dielectric (ILD) was determined for a 1-μm DLM process by using the dimensionless diagrams and considering the highest aspect ratios of the technology. Electrical characterization results confirm the good planarization capability of the BSG ILD
Keywords :
CVD coatings; borosilicate glasses; dielectric thin films; etching; integrated circuit technology; metallisation; 1 micron; B2O3-SiO2; BSG films; SOG sacrificial layer; VLSI multilevel interconnects; atmospheric CVD systems; chemical vapor deposition; double layer metalisation; etchback; interlevel dielectric; planarization; spin-on-glass; step coverage; void formation; Boron; CMOS technology; Dielectric films; Etching; Manufacturing processes; Planarization; Silicon; Surface resistance; Testing; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
Conference_Location :
Santa Clara, CA
Type :
conf
DOI :
10.1109/VMIC.1990.127909
Filename :
127909
Link To Document :
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