Title :
A high performance 16-Mb DRAM technology
Author :
Bakeman, P. ; Bergendahl, A. ; Hakey, M. ; Horak, D. ; Luce, S. ; Pierson, B.
Abstract :
A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstrated
Keywords :
DRAM chips; MOS integrated circuits; VLSI; integrated circuit technology; passivation; 0.5 micron; 16 Mbit; 16-Mb DRAM technology; 50 ns; DRAM cell size; DUV lithography; MINT cell structure; ULSI; access time; deep trench capacitor node; ease of integration; glass; key issues; packing density; polysilicon surface strap; smoothed PSG passivation; thick oxide collar; variable-size shallow trench isolation; yield;
Conference_Titel :
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIT.1990.110983
