DocumentCode
2705056
Title
A 1.28 μm2 bit-line shielded memory cell technology for 64 Mb DRAMs
Author
Kawamoto, Y. ; Kaga, T. ; Nishida, Tsutomu ; Iijima, S. ; Kure, T. ; Murai, F. ; Kisu, T. ; Hisamoto, D. ; Shinriki, H. ; Nakagome, Y.
fYear
1990
fDate
4-7 June 1990
Firstpage
13
Lastpage
14
Abstract
The technology used to fabricate high-speed and low-power 64-Mb DRAMs (dynamic random access memories) is described. The memory cell developed is a high-storage capacitance bit-line shielded stacked capacitor (STC) cell in which the storage capacitor is formed over the bit-line and a cylindrical storage node structure is used for low-voltage memory operation. The main features of the technology are low-resistance bit-line wiring to achieve short access time of the DRAM, and a simple process to fabricate the cylindrical storage node using poly-Si chemical vapor deposition (CVD) on polyimide layer to obtain large storage capacitance. The usefulness of the technology has been verified by fabricating an experimental 64-Mb DRAM
Keywords
DRAM chips; MOS integrated circuits; VLSI; chemical vapour deposition; integrated circuit technology; 64 Mb DRAMs; 64 Mbit; DRAMs; ULSI; access time; bit-line shielded memory cell technology; bit-line shielded stacked capacitor; cylindrical storage node structure; dynamic random access memories; features; high-speed; high-storage capacitance; low-power; low-resistance bit-line wiring; low-voltage memory operation; polyimide layer; simple process to fabricate;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on
Conference_Location
Honolulu, Hawaii, USA
Type
conf
DOI
10.1109/VLSIT.1990.110984
Filename
5727444
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