A high-performance stacked-CMOS SRAM cell by solid phase growth technique

Author

Uemoto, Y. ; Fujii, E. ; Nakamura, A. ; Senda, K.

fYear

1990

fDate

4-7 June 1990

Firstpage

21

Lastpage

22

Abstract

A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 10⁵ at the logic swing of 3 V, which could satisfy a 4-Mb SRAM with standby-current of 0.3 μA. The high performance has been attained as a result of enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a novel solid-phase growth (SPG) technique

Keywords

CMOS integrated circuits; SRAM chips; VLSI; integrated circuit technology; semiconductor growth; thin film transistors; 0.3 muA; 3 V; 4 Mbit; 4-Mb SRAM; SPG; ULSI; grain size; high-density; leakage-current; logic swing; low-standby-current; on/off ratio; p-channel TFT load; polycrystalline Si; polysilicon p-channel thin-film transistor; solid phase growth technique; stacked-CMOS SRAM cell;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on

Conference_Location

Honolulu, Hawaii, USA

Type

conf

DOI

10.1109/VLSIT.1990.110988

Filename

5727448