Title :
A manufacturable 2.0 micron pitch three-level-metal interconnect process for high performance 0.8 micron CMOS technology
Author :
Peng, S. ; Hsu, T.S.-H. ; Ray, G.W. ; Kuang-Yi Chiu, Kuang-Yi Chiu
Abstract :
Advanced CMOS ASICs require three-level-metal (TLM) capability, while double-level-metal (DLM) technology remains as the standard for logic circuits and high-performance memory applications. The challenges for multilevel interconnect systems are low defect density, high manufacturability, and product reliability. A TLM technology is described that has 2.0-μm-pitch first and second metals using aluminum alloy with 4% copper that meets these requirements. It has been demonstrated in the fabrication of a 90-MHz RISC CMOS CPU with a 1.4×1.4 cm2 chip size
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; integrated circuit technology; metallisation; microprocessor chips; reduced instruction set computing; 0.8 micron; 1.4 cm; 2 micron; 90 MHz; Al-Cu metallisation; CMOS ASICs; CMOS technology; RISC CMOS CPU; TLM; VLSI; challenges; chip size; high manufacturability; low defect density; multilevel interconnect systems; product reliability; three-level-metal interconnect process;
Conference_Titel :
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIT.1990.110990
