A Nanoscale CMOS SRAM Cell for High Speed Applications

The leakage current and process variation are drastically increased with technology scaling. In Conventional SRAM cell due to process variations, stored data can be destroyed during read operation. Therefore, leakage current of SRAM cell and stability during read operation are two important parameters in nano-scaled CMOS technology. To overcome these limitations and to increase the speed of conventional SRAMs, we have developed a read-static– noise-margin-free SRAM cell. The developed cell has six-transistors and uses two read/write-lines and two read/write-bit-lines during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The leakage current of new cell is 52% smaller than a conventional six-transistor SRAM cell. Simulation results shows proposed cell has correct operation during read/write and idle modes and is 45% faster than a usual six-transistor SRAM cell.