50% active-power saving without speed degradation using standby power reduction (SPR) circuit

High-speed and low-power are required for multimedia LSIs, since portability with battery operation is sometimes the key factor for multimedia equipment, while delivering giga operations per second (GOPS) processing power for digital video use. To understand circuit delay and power dissipation dependence on power supply voltage (V/sub DD/) and threshold voltage of MOSFETs (V/sub TH/), a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. A simulated delay dependence on V/sub DD/ and V/sub TH/ is presented. The same V/sub TH/ is chosen for nMOS and pMOS. It is shown that if V/sub TH/ is reduced to 0.3V, V/sub DD/ can be decreased down to 2V while maintaining the speed at V/sub TH/=0.7V and V/sub DD/=3V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.