DocumentCode :
2705457
Title :
NoC datapath for polymorphic processors in embedded systems
Author :
Weber, Joshua ; Oruklu, Erdal ; Saniie, Jafar
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear :
2010
fDate :
20-22 May 2010
Firstpage :
1
Lastpage :
6
Abstract :
Polymorphic processing has the goal of producing a processor combining the advantages of general purpose processing with the significant gains achievable by custom application specific computing. To achieve these ends a novel polymorphic processor architecture is presented. Incorporating networking on a chip (NoC) techniques into the datapath design has the potential to provide noticeable advantages when compared to a traditional processor datapath, especially for reconfigurable platforms such as FPGAs. This paper presents an architecture integrating NoC concepts into the design of a processor datapath in order to create a polymorphic processor. The paper will further explore and analyze the effect of topology choices and NoC design on the performance of polymorphic processors with specific focus on the impacts of NoC datapath integration.
Keywords :
embedded systems; multiprocessing systems; network-on-chip; reconfigurable architectures; NoC datapath; embedded systems; networking on a chip; polymorphic processors; reconfigurable platforms; topology; Computer architecture; Delay; Fabrics; Program processors; Registers; System-on-a-chip; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electro/Information Technology (EIT), 2010 IEEE International Conference on
Conference_Location :
Normal, IL
ISSN :
2154-0357
Print_ISBN :
978-1-4244-6873-7
Type :
conf
DOI :
10.1109/EIT.2010.5612135
Filename :
5612135
Link To Document :
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