Progress in speed power performance of bipolar technology by sub-10 keV B implantation into amorphized Si

Double polysilicon self-aligned bipolar n-p-n transistors have been fabricated with very narrow base widths by using very low-energy ion implantation of B at 2, 5, and (for comparison) 10 keV. To prevent channeling of B ions during implantation, several samples are amorphized by Ge ion implantation prior to the ¹¹B implant. A two-step annealing cycle with minimum thermal budget is described which meets the requirements for defect-free recrystallization of the amorphous layer and the damaged region while simultaneously avoiding, as far as possible, diffusion broadening of the B profile. These optimal conditions result in transistors with cutoff frequencies up to 28 GHz (at V_CB=3 V) and CML ring oscillators with 3.7-mW power consumption per gates at a minimum delay time of 35 ps/gate