Novel design and implementation for highly sensitive baseband protocol of Class-1 Generation-2 UHF RFID system

This paper presents novel transceiver baseband for EPC Global Calss-1 Generation-2 compliant RFID reader. The main challenge in RFID reader design is the detection of the backscattered signal from tag. Noise, whose power depends on the environment, can degrade the detection performance. To overcome the environmental noise, the look-up-table based RCT (Raised Cosine Transform) pulse shaping method is proposed for the transmitter architecture. Furthermore the detection of the signal from tag at receiver is impeded by phase noise. To fight these various disturbances, Rising-Falling Edge-detection based Synchronizer (RFES) is proposed as the secondary synchronizer for RFID receiver baseband. This is the first architecture for signal detection in RFID, applying frequency synchronization technique in baseband to reduce the BER, and thus leading to improved performance compared with Industrial readers. The proposed schemes is implemented in Simulink and Verilog; and validated through FPGA. Details of the implementation of the transceiver baseband on an FPGA are explained. Measurement data show that proposed Lookup table based pulse shaping method achieved 4 dB improvement in adjacent band power suppression. Furthermore, introduce of a secondary synchronizer in baseband improves the sensitivity by 3 dB compared with traditional state-of-art readers in industry.