Merged complementary BiCMOS for logic applications

The deficiencies of BiCMOS logic are analyzed, and the addition of a high-performance vertical pnp to the BiCMOS technology, henceforth called complementary BiCMOS technology, is considered as a solution. It is suggested that density problems associated with BiCMOS logic can be alleviated by replacing the conventional BiCMOS logic circuit, i.e. the `totem-pole´ circuit, with a simpler complementary emitter follower circuit. This circuit allows the use of a merged bipolar-FET device structure as well as a common subcollector for the pnp, which further increases density. Another benefit of the common subcollector is that it reduces the process complexity associated with the addition of the vertical pnp. High performance is demonstrated with results from a test circuit with delays of 250 pS with 0.3 pF loading