DocumentCode
2705788
Title
A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices
Author
Johnson, E.D. ; Hook, T.B. ; Bertsch, J.E. ; Taur, Y. ; Chen, C.L. ; Shin, Hee Jung ; Ramaswamy, Srini ; Edenfeld, A. ; Alcorn, C.
fYear
1990
fDate
4-7 June 1990
Firstpage
89
Lastpage
90
Abstract
A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while keeping the CMOS devices at 3.3 V for reliable operation. With such a circuit, performance gain over CMOS is achieved at a reduced channel length and voltage. This demonstrates the feasibility of scaling BiCMOS technology to reduced channel length and power supply voltage
Keywords
BIMOS integrated circuits; CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; 0.5 micron; 15 GHz; 3.3 V; BiCMOS technology; CMOS base process; CMOS-compatible heat cycles; channel length; cutoff frequency; level-shifted BiCMOS circuit techniques; performance degradation; performance gain; power supply voltage; scaling; single-polysilicon npn transistor;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on
Conference_Location
Honolulu, Hawaii, USA
Type
conf
DOI
10.1109/VLSIT.1990.111022
Filename
5727482
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