Advanced device process technology for 0.3 μm self-aligned bipolar LSIs

Author

Tamaki, Yoichi ; Shiba, Takeo ; Ogiwara, Itaru ; Kure, Tokuo ; Ohyu, Kiyonori ; Nakamura, Tohru

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1990

fDate

17-18 Sep 1990

Firstpage

166

Lastpage

168

Abstract

A novel method is developed for forming a shallow emitter/base and graft base suitable for 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove, isolated sidewall base contact structure) transistors are 44 μm² in size, and have a cutoff frequency (f_T) of 38 GHz and an ECL (emitter coupled logic) gate delay time of 27 ps. BF₂ ion-implantation was used to form shallow intrinsic base regions. As diffusion from polysilicon by rapid thermal annealing was used to form a shallow emitter profile. A shallow graft base was formed using an improved self-aligned boron diffusion technique. The reduction of parasitic capacitance improves the performance of advanced bipolar devices

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; ion implantation; large scale integration; 0.3 micron; 0.5 micron; 27 ps; 38 GHz; BF₂ ion-implantation; Si:BF₂; U-SICOS; U-groove; advanced bipolar devices; cutoff frequency; emitter coupled logic; isolated sidewall base contact structure; polysilicon; rapid thermal annealing; self-aligned bipolar LSIs; shallow emitter/base; shallow graft base; shallow intrinsic base regions; Circuits; Delay effects; Electrical resistance measurement; Impurities; Isolation technology; Large scale integration; Leakage current; Parasitic capacitance; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1990.171154

Filename

171154