A new aspect on mechanical stress effects in scaled MOS devices

MOS device characteristics were investigated by imposing external mechanical stress on a Si chip and experimental results are physically evaluated using mechanical stress simulation. Deviation of device characteristics due to external stress is strongly dependent on gate length. This is due to a redistribution of stress in the channel by external stress, which is a strong function of length. That is, the shorter the gate length, the smaller the surface stress due to external stress along the channel. Experiments on hot-carrier injection shows that external compressive stress longitudinal to the current flow increases the capture rate of hot electrons in SiO₂ and that tensile stress has less influence in both NMOS and PMOS. In deep-submicron devices, the external stress effect tends to be less. This will be favorable for final fabrication like packaging