Manufacturable triple level metal technology for submicron CMOS

Author

Paulson, W. ; Klein, J. ; Woo, M. ; Kobayashi, T. ; Hendrix, R. ; Travis, E. ; Pintchovski, F. ; See, Y.C.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1990

fDate

12-13 Jun 1990

Firstpage

407

Lastpage

409

Abstract

The triple-level-metal (TLM) module of a submicron CMOS technology with (titanium) salicided devices is discussed. The key technology features of the module include the use of conformal BPSG for enhanced planarization, a TiN barrier layer under M1, plasma-dry-tapered contacts and vias, and TiN antireflection coatings for metal patterning. Large-area test structures for each TLM component were used to develop and evaluate the processes. Electrical measurements and physical analysis are presented for these components

Keywords

CMOS integrated circuits; integrated circuit manufacture; integrated circuit technology; metallisation; B2O3-P2O5-SiO2; TiN antireflection coatings; TiN barrier layer; TiSi₂; conformal BPSG; metal patterning; planarization; plasma-dry-tapered contacts; salicided devices; submicron CMOS; triple level metal technology; vias; CMOS technology; Coatings; Contacts; Manufacturing; Planarization; Plasma devices; Plasma materials processing; Plasma measurements; Tin; Titanium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1990.127914

Filename

127914