A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cell

Author

Riemenschneider, B. ; Esquivel, A.L. ; Paterson, J. ; Gill, M. ; Lin, Shunjiang ; Schreck, J. ; McElroy, D. ; Truong, P. ; Bussey, R. ; Ashmore, B. ; McConnell, M. ; Stiegler, H. ; Shah, P.

fYear

1990

fDate

4-7 June 1990

Firstpage

125

Lastpage

126

Abstract

A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm² cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 μm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 μm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 μm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle

Keywords

CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 0.8 micron; 18 V; 2.0 micron; 4 Mbit; 5 V; ACEE technology; CMOS process; LOCOS isolation; VLSI; array technology; bitlines; diode isolation; effective separation; flash EEPROM; integrated process flow; low-voltage isolation; minimum lithographic feature sizes; process technology; silicided contacts; single-power-supply; single-transistor advanced contactless EEPROM; sublithographic remote tunnel diode structure;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on

Conference_Location

Honolulu, Hawaii, USA

Type

conf

DOI

10.1109/VLSIT.1990.111040

Filename

5727500